1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) circuit.
2. Description of the Related Art
When a superheterodyne receiver is configured into a synthesizer system, the local oscillating signal of the receiver is formed by a PLL circuit. The PLL circuit is generally formed as indicated by reference numeral 10 in FIG. 6. Specifically, in the PLL circuit 10, an oscillating signal SVCO of a VCO (voltage controlled oscillator) 11 is supplied to a variable frequency divider circuit 12 to be frequency-divided into a frequency-divided signal SDIV of a 1/N (N is a positive integer) frequency. The frequency-divided signal SDIV is supplied to a phase comparator circuit 13. In addition, a reference signal SREF of a frequency fREF serving as a reference is supplied to the phase comparator circuit 13.
The phase comparator circuit 13 compares the phases of the frequency-divided signal SDIV and the reference signal SREF with each other. The comparison output of the phase comparator circuit 13 is supplied to a charge pump circuit 14, from which a phase comparison output whose pulse width changes in such a manner as to correspond to a phase difference between the frequency-divided signal SDIV and the reference signal SREF is extracted. Then, the comparison output is supplied to a loop filter 15, from which a direct-current voltage VC whose level changes in such a manner as to correspond to the phase difference between the frequency-divided signal SDIV and the reference signal SREF is extracted. The direct-current voltage VC is supplied as a control voltage for controlling an oscillating frequency fVCO to the VCO 11.
As a result, in a steady state, the oscillating frequency fVCO of the VCO 11 isfVCO=N·fREF
Thus, the oscillating frequency fVCO of the VCO 11 can be varied by changing a frequency division ratio N.
Thus, conversion of frequency of a received signal can be performed using the oscillating signal SVCO (or a frequency-divided signal of the oscillating signal SVCO) of the VCO 11 as a local oscillating signal, and reception frequency can be varied by changing the frequency division ratio N or the reference frequency fREF. That is, reception of a synthesizer system can be performed.
The following, for example, are related art documents.
For the related art regarding the present information, reference should be made to Japanese Patent Laid-Open No. 2001-156629, Japanese Patent Laid-Open No. Hei 9-93125 and Japanese Patent Laid-Open No. Hei 11-308101.